Lecture notes for week 1 day 2

this lecture will be on the following :- system bus, interconnection structures (bus structure and bus type ) interrupts and instruction cycle

Buses: it is a communication ppathway connecting two or more devices. it is a shared transmission medium.

•There are a number of possible interconnection systems
•Single and multiple BUS structures are most common
•e.g. Control/Address/Data bus (PC)
•e.g. Unibus (DEC-PDP)
a system bus consists, typically, of from about 50 to hundreds of separate lines, each line is assigned a particulat meaning or function.
any bus line can be classigied into 3 functional groups:- data,address,control
data bus:- 

•Carries data
—Remember that there is no difference between “data” and “instruction” at this level
•Width is a key determinant of performance
—8, 16, 32, 64 bit
address bus:-
 

 

•Identify the source or destination of data
•e.g. CPU needs to read an instruction (data) from a given location in memory
•Bus width determines maximum memory capacity of system
—e.g. 8080 has 16 bit address bus giving 64k address space
control bus :-
 

 

•Control and timing information
—Memory read/write signal
—Interrupt request
—Clock signals
bus interconnection structure:
see the figure 3.16 .
bus types:

•Dedicated
—Separate data & address lines
•Multiplexed
—Shared lines
—Address valid or data valid control line
—Advantage – fewer lines
—Disadvantages
–More complex control
–Ultimate performance
 

 

•What do buses look like?
—Parallel lines on circuit boards
—Ribbon cables
—Strip connectors on mother boards
–e.g. PCI
—Sets of wires

the top level view of computer component:

instruction cycle:

•Two steps:
—Fetch
—Execute
Fetch cycle:

•Program Counter (PC) holds address of next instruction to fetch
•Processor fetches instruction from memory location pointed to by PC
•Increment PC
—Unless told otherwise
•Instruction loaded into Instruction Register (IR)
•Processor interprets instruction and performs required actions
execute cycle:

•Processor-memory
—data transfer between CPU and main memory
•Processor I/O
—Data transfer between CPU and I/O module
•Data processing
—Some arithmetic or logical operation on data
•Control
—Alteration of sequence of operations
—e.g. jump
•Combination of above
Interrupts:

•Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
•Program
—e.g. overflow, division by zero
•Timer
—Generated by internal processor timer
—Used in pre-emptive multi-tasking
•I/O
—from I/O controller
•Hardware failure
—e.g. memory parity error
interrupt cycle:

 

•Added to instruction cycle
•Processor checks for interrupt
—Indicated by an interrupt signal
•If no interrupt, fetch next instruction
•If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler routine
—Process interrupt
—Restore context and continue interrupted program
transfer of control via interrupts:
instruction cycle with interrupts:
state diagram of instruction cycle with interrupts:
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